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UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of FPGA and ASIC – resulting also in significant quality improvement.

This project houses the (to be confirmed) IEEE Standards Association Proposed PAR (Project Authorization Request) entitled:

Re-Use Library Abstraction (RULA) as a means to accelerate library adoption by decreasing library learning uptake time.

Microsite for the IEEE SA OPEN Infrastructure Community

A [WIP] patch for github.com/chaoss/grimoirelab-elk with support for data retrieved from perceval-osf