Explore projects
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uvvm / UVVM
OtherUVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of FPGA and ASIC – resulting also in significant quality improvement.
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Robert Teese / LivePhoto
Creative Commons Attribution Non Commercial Share Alike 4.0 InternationalUpdated -
1451 / 1451.0-schema
BSD 3-Clause "New" or "Revised" LicenseUpdated -
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Robert Teese / vignette-studio-ii
GNU General Public License v3.0 or laterUpdated -
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Blog with challenges and opportunities in the Electric Mobility ecosystem
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Open at RIT / Mystic / Mystic Evoker
GNU Affero General Public License v3.0A frontend client for Mystic, calling upon its magical services to manifest results
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MH Sobuj / basketodum
MIT LicenseUpdated -
Jason Todd / Mystic Evoker
GNU Affero General Public License v3.0A frontend client for Mystic, calling upon its magical services to manifest results
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Example plain HTML site using GitLab Pages: https://pages.gitlab.io/plain-html
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infra / IEEE SA OPEN Hugo Theme
MIT LicenseHugo theme for IEEE SA OPEN websites under the IEEE SA OPEN umbrella. This includes all CSS, images, layouts, and other related assets.
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Open at RIT / Mystic / Mystic
GNU Affero General Public License v3.0Your home for open source in your community
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Open Up / openup.ieee-saopen.org
MIT LicenseA gitlab pages site for Open Up. It uses Hugo for static site generation and templating.
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