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The following project contains open source materials that will be referenced by the IEEE 1076 standard.

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UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of FPGA and ASIC – resulting also in significant quality improvement.

This project houses the (to be confirmed) IEEE Standards Association Proposed PAR (Project Authorization Request) entitled:

Re-Use Library Abstraction (RULA) as a means to accelerate library adoption by decreasing library learning uptake time.

This project is mostly written in Python, and has a few different subprojects.

The following project contains open source materials that will be referenced by the IEEE 1076 standard.

This is the IEEE SA OPEN live site using GitLab Pages & Gatsby 5.3 (as of 2/6/2023).

The default URL for this Pages site for this project is: https://saopen.ieee-saopen.org/

gitlab pages site for SCaLE 19x event hosted by IEEE SA OPEN

A [WIP] patch for github.com/chaoss/grimoirelab-elk with support for data retrieved from perceval-osf

FOSSRIT Website Mirror (manual; for tetsing)

SA Open IEEE testing site using GitLab Pages: https://saopen.ieee-saopen.org/saopen-devops/ Gatsby 5.3 version (as of 2/6/2023)

Microsite for the IEEE SA OPEN Infrastructure Community

This project is mostly written in Python, and has a few different subprojects.

The following project contains open source materials that will be referenced by the IEEE 1076 standard when it is approved and published.

The following project contains open source materials that will be referenced by the IEEE 1076 standard.

The following project contains open source materials that will be referenced by the IEEE 1076 standard when it is approved and published.