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uvvm / UVVM
OtherUVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of FPGA and ASIC – resulting also in significant quality improvement.
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Open at RIT / Mystic / Mystic Evoker
GNU Affero General Public License v3.0A frontend client for Mystic, calling upon its magical services to manifest results
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InsLife / IEEE C57.91 Thermal Models
BSD 3-Clause "New" or "Revised" LicenseUpdated -
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Devashish Chaudhary / assert_manager
GNU General Public License v3.0 or laterThis project is mostly written in Python, and has a few different subprojects.
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ShEx / spec
Apache License 2.0Updated -
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Josh Gay / funsearch
Apache License 2.0Updated